1. Field of the Invention
The present invention concerns a method of forming an SOI structure and a semiconductor memory device using the forming technique. SOI has been used as a structure for electronic parts such as semiconductor devices and the present invention can be utilized as a method of forming various kinds of SOI structures.
More specifically, it can be used, for example, to SRAM or EEPROM. In EEPROM, it relates, in particular, to a method of manufacturing a non-volatile memory device in which a control gate electrode layer is laminated by way of an insulator film on a floating gate electrode layer.
2. Description of the Prior Art
The SOI (silicon on insulator) structure has been utilized mainly in the field of electronic materials by a method of forming various kinds of semiconductor devices to a silicon portion disposed on an insulator layer.
As one of means for forming the SOI structure, it has been known a technique for bonding a substrate to another silicon substrate formed with an insulator portion on the side of the insulator portion and polishing the silicon substrate thereby providing a structure in which the silicon portion is present on the insulator portion. It is generally referred to as a bonded SOI or the like.
Since the bonded polished type SOI structure and a process therefor enables high integration of electronic materials and makes it possible to assemble devices above and below the silicon portion, it contributes to increase of the integration degree of IC or the like.
Description will now be made to a method of forming the bonded SOI structure with reference to FIG. 1-A to FIG. 1-G (refer to M. Hashimoto et. al. "Low Leakage SOIMOSFETs Fabricated Using a Wafer Bonding Method" in Extended Abstracts of the 21st Conference on Solid State Devices and Material 15, Tokyo, 1989, pp. 89-92 n).
As shown in FIG. 1-A, one surface of a silicon substrate 1 (highly flattened silicon wafer is generally used and referred to as a substrate A) is patterned by using photolithography or etching technology to form a recess at a depth of 1500 A or smaller.
Then, an insulator portion 2 is formed by forming an SiO.sub.2 film on the surface by means of CVD or the like. Thus, a structure in which the insulator portion 2 is formed on one side of the silicon substrate 1 is obtained as shown in FIG. 1-B. The insulator portion 2 is formed as a film having unevenness as illustrated in the figure in accordance with the surface shape of the patterned silicon substrate 1.
Further, a polysilicon film 3 is formed to a thickness of about 5 um on the insulator portion 2, for example, by CVD. Thus the structure shown in FIG. 1-C is obtained. The polysilicon film 3 is provided for forming a highly smooth bonding surface upon bonding a separate substrate 4 (substrate 4 shown in B in FIG. 1-E) in the subsequent step.
Then, the surface of the polysilicon film 3 is polished to flatten, to attain a highly smooth surface. In this case, the thickness of the polysilicon film 3 as a remaining film is made to a thickness of 3 um or less.
Another substrate 4 (hereinafter referred to as substrate B) is brought into a close contact with the polished surface of the polysilicon film 3. Both of the surfaces are joined in close pressure bonding to obtain a joined structure as shown in FIG. 1-E. It is generally said that firm joining is attained due to hydrogen bonds present between both of the surfaces. Usually, they are thermally joined by heating to attain an extremely firm bonding. The bonding strength is generally greater than 200 kg/cm.sup.2 and, sometimes, reaches as great as 2000 kg/cm.sup.2. As another substrate 4 (substrate B) to be bonded, the same silicon substrate as the substrate 1 (substrate A) is usually employed, because a failure may be caused unless physical property such as thermal expansion coefficient is equal between them since they are often put to a heating step subsequent to the bonding. If there is no such problem, another substrate 4 is not necessarily a silicon substrate since this functions only as a support bed in the prior art, for example, shown in the drawing. However, in a case of forming a device also on the another substrate 4 (substrate B) to be appended, it has to be a semiconductor substrate capable of forming a device.
Then, the substrate 1 is ground so as to leave a silicon portion of the substrate 1 to about 5 um or less as the remaining film to attain a structure shown in FIG. 1-F. FIG. 1-F is turned from state in FIG. 1-E, because the structure is turned upside to down to situate the substrate 1 above for this grinding or for the subsequent selective polishing.
Then, selective polishing is applied. In this case, polishing of precious finishing is applied till the insulator portion 2 is just exposed. This provides a structure as shown in FIG. 1-G in which a silicon portion 10 is present on the insulator portion 2 being surrounded with undulating insulator portion 2. The silicon portion 10 forms a SOI film. To a structure in which the silicon portion 10 is present on the insulator portion 2 (SOI structure), various kinds of devices are formed to the silicon portion 10 (SOI film). As shown in FIG. 1-G, since each of the silicon portions 10 is surrounded with the insulator portion 2, a structure in which device isolation is attained from the first is provided.
Further, in a method of manufacturing the SOI substrate as described above, since the film thickness 10 in FIG. 1-G varies within a wafer surface, the thickness of an inland single crystal silicon thin film formed to or required pattern also varies.
Further, selective polishing is applied till the boundary between the silicon wafer and the silicon oxide film is exposed in order to obtain a required pattern for the single crystal silicon thin film. In this case, since an over polishing is required to some extent, the surface of silicon is exposed to an alkaline polishing solution for a long period of time, to roughen the silicon surface. If a TFT (thin film transistor) is formed on the roughened silicon surface, a device with good characteristics can not be obtained since the reliability of a gate insulator film is lowered.
Further, in the SOI process utilizing the bonding polishing method as described above or an electrostatic pressure bonding method, since various kinds of devices can be assembled to the surface and the rear face of the SOI portion (the silicon portion 10 in FIG. 1-G), the mounting density can be increased. By adopting this technology, the size of a memory cell, for example, DRAM can be reduced. However, although the density of a circuit such as a memory cell has been intended to increase in the prior art, the merit of this technique is not effectively utilized for peripheral circuits. For instance, referring to a memory device such as a DRAM or SRAM, although it has been considered to reduce the size of the memory cell by using the SOI technology, the SOI technology is not always utilized for other peripheral circuits and, for example, it has not been conducted to increase the density for the transistor as the peripheral circuit, thereby improving the performance (for example, increasing the operation speed).
Further, for the method of forming a memory device such as EEROM, electric characteristics can be improved outstandingly by applying the polishing method used for SOI.
That is, as shown in FIG. 2, when a floating gate electrode layer is formed, the surface is not flattened but pointed protrusions 25 are formed. Then, an electric field is concentrated to a portion where the protrusions 15 are present in this structure.
Accordingly, in a second gate insulator film between the floating gate electrode 13 and the control gate electrode 14, there is a portion where the thickness is decreased by the protrusions 15. If LSI is manufactured in such a state and applied with a voltage, the electric field is concentrated to a portion where the protrusions 15 are present. Then, electrons in the floating gate electrode are extracted by the electric field applied to the control gate electrode due to the concentration of the electric field, to result in signal data possessing characteristic, thereby bringing about a problem incapable of maintaining the threshold value of a memory transistor at a high level.